In conventional integrated circuit devices, for example, memory devices such as dynamic random access memory (DRAM) devices, that include resistors, the resistors are typically formed of impurity-doped polysilicon because changing the doping concentration of the impurities can control a resistance of the resistor. Referring now to FIG. 1, a conventional process of fabricating conventional integrated circuit devices including resistors will be discussed.
As illustrated in FIG. 1, a lower interlayer dielectric layer 3 is formed on an integrated circuit substrate 1. The substrate 1 is divided into a cell array region A and a peripheral circuit region B. In the cell array region A, the lower interlayer dielectric layer 3 is patterned to form a contact hole that exposes at least a portion of a surface of the integrated circuit substrate 1. A conductive material may be deposited in the contact hole to form a buried contact plug 5. A first etch stop layer 7 and a first interlayer dielectric layer 9 are formed on the buried contact plug 5 and the lower interlayer dielectric layer 3. In the cell array region A, the first interlayer dielectric layer 9 and the first etch stop layer 7 are patterned to form a pad contact hole that exposes at least a portion of the buried contact plug 5. Simultaneously, in the peripheral circuit region B, the first interlayer dielectric layer 9 may be removed. A conductive material may be deposited in the pad contact hole to form a pad contact plug 11. In the peripheral circuit region B, the conductive material may be removed so that at least a portion of the lower interlayer dielectric layer 3 is exposed. An impurity-doped polysilicon layer is formed on a surface of the integrated circuit substrate 1 and patterned to form a resistor 15 in the peripheral circuit region B. Simultaneously, in the cell array region A, the impurity-doped polysilicon layer may be removed to expose the first interlayer dielectric layer 9 and the pad contact plug 11. A second etch stop layer 17 is formed on a surface of the integrated circuit substrate 1 including the resistor 15. A lower electrode 18 is formed on the integrated circuit substrate 1. The lower electrode 18 may be electrically coupled to the pad contact plug 11 through the second etch stop layer 17. A dielectric layer 19 and an upper electrode 21 are conformally formed on the lower electrode 18 to form a capacitor. In the peripheral circuit region B, the upper electrode 21 may be removed using, for example, a patterning process. A second interlayer dielectric layer 23 may be formed on the capacitor and the second etch stop layer 17. In the peripheral circuit region B, the second interlayer dielectric layer 23 and the second etch stop layer 17 are sequentially patterned to form a metal contact hole 24 that exposes at least a portion of the resistor 15.
An ohmic layer 26 is formed in the bottom of the metal contact hole 24 that may reduce a resistance difference between the metal of the metal contact plug and the polysilicon of the resistor 15. In particular, a metal layer, for example, titanium, may be conformally formed in the metal contact hole 24 and, for example, a rapid thermal process may be performed at a temperature greater than about 600 degrees Celsius. The polysilicon of the resistor 15 may react with the metal layer to form the ohmic layer 26 of metal silicide, for example, titanium silicide. A metal contact plug may be formed in the metal contact hole 24 on the ohmic layer 26. However, during the rapid thermal process at the temperature greater than about 600 degrees Celsius, the dielectric layer 19 of the capacitor in the cell array region may be damaged, which may cause a leakage current of the capacitor to increase during operation of the integrated circuit device. Accordingly, the overall reliability of the integrated circuit device may be reduced.